Multi-level power supply system for a complementary metal oxide semiconductor

ABSTRACT

There is provided a method that includes comparing a voltage level (Vs 1 ) of a lower voltage supply bus to a voltage level (Vs 2 ) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs 2 &lt;Vs 1 . The lower and higher voltage supply busses provide power to a complementary metal oxide semiconductor (CMOS) circuit. There is also provided a circuit that employs the method.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. patent applicationSer. No. 12/145,622, filed Jun. 25, 2008, which is a continuation ofU.S. patent application Ser. No. 10/867,094, filed Jun. 14, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multi-level power supply, and moreparticularly, to a technique of managing a multi-level power supply toavoid a latch-up of a complementary metal oxide semiconductor (CMOS)circuit.

2. Description of the Related Art

A semiconductor integrated circuit may include numerous active andpassive devices. For example, the circuit may include active devicessuch as transistors, diodes, and thyristors, and passive devices such ascapacitors, resistors and inductors. During manufacturing, extra devicesmay be inadvertently created. These extra devices are referred to asparasitic devices. The parasitic devices are not usually turned onduring normal operation of the circuit, and current gain of parasiticpnp and npn bipolar transistors is normally very small.

However, in some circumstances, such as during a power-on period, theparasitic devices can be activated. This is because in an electronicsystem may include more than one level of power supply. During thepower-on period, if a power supply with a lower voltage level comes onearlier than a power supply with a higher voltage level, a p-n junctioncould be forward biased. A parasitic pnp and npn, together, form ap-n-p-n thyristor. If the thyristor is connected between a power supplyand an electrical ground, forward biasing of the p-n junction turns onthe parasitic pnp and npn devices, which results in a high current flowfrom power supply to ground. A latch-up is a situation where thethyristor is triggered during the power-on period and causes a highcurrent to flow from the power supply to ground. As a result of suchhigh current, other circuits can be damaged, e.g., a melt down of metalwires. A detailed description of latch-up can be found in R. R.Troutman, “Latchup in CMOS Technology”, Kluwer Academic Publishers,Boston, 1986.

A CMOS circuit built on a bulk silicon wafer is susceptible to latch-up.When latch-up conditions are met, a low-impedance path, e.g., throughp-n-p-n junctions, is established between a power supply and ground.Once latch-up occurs, not only may circuits cease to function, but thelatch-up may also induce catastrophic failure from joule heating.Ordinarily, the latch-up cannot be stopped unless power is removed andthe circuits are reactivated.

To power-on a system having multiple-voltage supplies, if one supply isramped up faster (or slower) than another, it is possible that some p-njunctions may be unintentionally forward biased, and the system couldenter the latch-up situation. A body of a MOS device is an area beneatha channel of the MOS device and between a source and drain of thedevice. A body of a p-type metal oxide semiconductor (pMOS) device istied to a higher voltage level than that of the pMOS device'ssource/drain junctions. A guard ring is a diffusion ring that surroundsthe pMOS device. The guard ring has an opposite doping polarity to thatof the body, and is reverse biased to isolate the pMOS device. Duringpower-on, if the higher voltage supply is ramped up more slowly than thelower voltage supply, a p-type source/drain junction may be forwardbiased to an n-type body, which could result in a latch-up, especiallyif guard rings are not installed.

A well is an isolated body region. In a CMOS circuit, in order to savesilicon area, it is desirable to place all pMOS devices in a singlen-well and to bias the n-well to a highest voltage level. Accordingly,the n-well is typically tied to a supply having a highest voltage level.If, instead of employing a single n-well, multiple n-wells are employed,then each of the multiple n-wells must be connected to a respectivebias, and extra silicon area, as compared to a case of a single n-well,is required to accommodate well-to-well spacing.

However, in order to avoid latch-up, the sharing of wells is oftenprohibited. In a dynamic random access memory (DRAM), a higher voltagesupply is generated from a lower voltage supply by using a charge pumpand a voltage regulator. The higher voltage supply is inherently rampedup much later than the lower voltage supply. DRAMs typically include aboost word supply line (Vpp) for boosting a voltage of a selected wordline in order to achieve a proper access time for the selected wordline. The boost word supply line Vpp is also typically the highestvoltage level in the DRAM, for example, Vdd=1.5 volts and Vpp=3.0 volts.During a power-on sequence, after Vdd is ramped up, there is a delay ofabout 10 nanoseconds (ns) to 100 ns until the boost word line supply Vppis ramped up. Since, in order to avoid latch-up, the sharing of wells isprohibited, a larger chip area is required than there would be if sharedwells were permitted.

SUMMARY OF THE INVENTION

There is a need for an improved technique for preventing latch-up of amulti-level power supply CMOS system during power-on.

Additionally, there is a need for such a technique that also permits asharing of wells by pMOS devices.

These and other objects are achieved by a method that includes comparinga voltage level (Vs1) of a lower voltage supply bus to a voltage level(Vs2) of a higher voltage supply bus, and routing current from the lowervoltage supply bus to the higher voltage supply bus if Vs2<Vs1. Thelower and higher voltage supply busses provide power to a complementarymetal oxide semiconductor (CMOS) circuit. There is also provided acircuit that employs the method.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic of a level shifter circuit for converting asignal level from Vcc to Vdd, and that includes a power supply switchsystem for preventing latch-up.

FIG. 1B is an illustration of a portion of the circuit of FIG. 1Ashowing a possible layout thereof.

FIG. 1C is an illustration of a portion of the circuit of FIG. 1Ashowing a possible alternative layout.

FIG. 2 is an illustration of a circuit in which a CMOS inverter is builtin a triple-well, has a parasitic p-n-p-n latch-up path, but includes apower supply switch system for preventing latch-up.

FIG. 3A is a schematic of a microelectronic circuit system that includesa switch module for preventing latch-up, and that receives power from aplurality of independent external power supplies.

FIG. 3B is a schematic of a microelectronic circuit system that includesa switch module for preventing latch-up, and that receives power from asingle external power supply.

FIG. 4 is a schematic of a system having a plurality, i.e., “n”, ofsupply levels and switch modules for preventing latch-up.

FIG. 5 is a schematic of an embodiment of a CMOS switch module forshorting two supply levels.

DESCRIPTION OF THE INVENTION

A power supply switch system utilizes a power switch to, under certaincircumstances, route current from a lower voltage supply bus to a highervoltage supply bus. More specifically, if the higher voltage supply busis not ready, e.g., is at a lower voltage level than that of the lowervoltage supply bus, the power supply switch system routes current fromthe lower voltage supply bus to the higher voltage supply bus, thusavoiding latch-up of a CMOS device that is being powered by the voltagesupply busses.

A voltage sensor, e.g., a comparator, is associated with the switchmodule. The comparator senses voltage levels on the supply busses and,based on a relationship between the voltage levels, determines “ON/OFF”states of the power switch. When the higher voltage supply bus is notavailable or is not ready, the switch is turned ON so that current isrouted from the lower voltage supply bus to the higher voltage supplybus. The current continues until the higher voltage supply level isestablished, and then the switch is turned OFF. The power supply switchsystem can be extended to accommodate a system having more than twovoltage supply levels. Also, the switch and the comparator can be ofrelatively small size, e.g., less than 0.1% of a semiconductor chiparea.

FIG. 1A is a schematic of a level shifter circuit 100, which is designedto shift an input signal level of Vdd to an output signal level of Vcc,where Vdd<Vcc. Circuit 100 includes pMOS devices p1, p2 and p3, and nMOSdevices n1, n2 and n3. Circuit 100 also includes a power supply switchsystem 105 that provides voltage levels Vcc and Vdd to respectivevoltage busses. For proper operation, circuit 100 requires Vcc>Vdd.

The input signal IN has a voltage swing from ground to Vdd, and isconverted to the output signal OUT having a voltage swing from ground toVcc. During normal operation of circuit 100, Vcc is greater than Vdd,and therefore pMOS devices p1 and p2 are masked by a thick oxide mask105. pMOS devices p1 and p2 each have a body that is tied to the Vccbus, and pMOS device p3 has a body tied to the Vdd bus.

FIG. 1B is an illustration of a portion of circuit 100 showing apossible layout thereof. The layout of FIG. 1B has two n-wells, namelyn-wells NW1 and NW2. pMOS devices p1 and p2 are located within n-wellNW1, which is biased by Vcc, and p-MOS device p3 is located in n-wellNW2, which is biased by Vdd.

FIG. 1C is an illustration of a portion of circuit 100 showing apreferred layout. To save area, as compared to the layout of FIG. 1B,all of pMOS devices p1, p2 and p3 are placed inside one n-well, i.e.,n-well NW1, and their bodies are all tied to the Vcc bus. This layoutcould save area significantly, especially when there are many such mixedvoltage circuits.

Power supply switch system 105 ensures that the higher voltage supplybus, in this case the Vcc bus, will, under certain circumstances,receive current from the lower voltage supply bus, i.e., the Vdd bus.Routing of current from the lower voltage supply bus to the highervoltage supply bus avoids p-n junction forward bias within circuit 100,and so, prevents a latch-up of circuit 100. Thus, circuit 100 can beconfigured with a layout as shown in either of FIG. 1B or 1C.

FIG. 2 is an illustration of a circuit 200 in which a CMOS inverter isbuilt in a triple-well. Circuit 200 includes a power supply switchsystem 205 that provides voltage levels Vcc and Vdd to respectivevoltage busses.

In circuit 200, to save area, all pMOS devices are located within acommon n-well. The n-well is biased to its highest supply, e.g., Vcc. IfVcc were not available, a parasitic pnp bipolar device Q2 would have aforward biased emitter-base junction that would suddenly increase thegain of device Q2 and induce a latch-up. Eventually, a high level ofcurrent would flow in a path from the Vdd supply bus, through Q2, andthen through Q1 to ground. This path is known as a parasitic p-n-p-nlatch-up path. Power supply switch system 205 provides voltages Vcc andVdd in an orderly manner to prevent the latch-up of circuit 200.

FIG. 3A is a schematic of a microelectronic circuit system 300A. System300A provides voltage levels Vs1 and Vs2 to voltage busses 375 and 380,respectively, where under normal, proper, operating conditions, Vs2 is ahigher voltage level than Vs1. System 300A includes a power supplyswitch system 370 that, in turn, includes a switch module 360, a voltagecomparator 330 and two sets of interconnects 340 and 350.

Voltage comparator 330 receives, as inputs, Vs1 and Vs2, and provides anoutput SW that indicates a relationship between Vs1 and Vs2. Whenvoltage comparator 330 senses that Vs2 is greater than or equal to Vs1,then SW=0. Conversely, when voltage comparator 330 senses that Vs2 isless than Vs1, then SW=1. SW is provided from voltage comparator 330 toswitch module 360.

Switch module 360 receives SW and, based on the state of SW, controlswhether current is permitted to flow from Vs1 bus 375, through switchmodule 360, to Vs2 bus 380. If SW=0, then switch module 360 is turnedOFF, i.e., opened, and current does not flow from Vs1 bus 375 to Vs2 bus380. If SW=1, then switch module 360 is turned ON, i.e., closed, andcurrent flows from Vs1 bus 375 through interconnect lines 350, switchmodule 360 and interconnect lines 340, to Vs2 bus 380. The operation ofpower supply switch system 370 is summarized in Table 1.

TABLE 1 Relationship between Switch Vs1 and Vs2 SW module 360 CurrentControl Vs2 ≧ Vs1 0 Opened Current does not flow from Vs1 bus 375 to Vs2bus 380 Vs2 < Vs1 1 Closed Current flows from Vs1 bus 375 to Vs2 bus 380

System 300 includes two power supply pads 310 and 320 that representconnections to two separate external power supplies (not shown) forsupplying power to Vs1 bus 375 and Vs2 bus 380. By design, Vs2 isintended to be greater than Vs1. However, during power-on, either of Vs1or Vs2 may be ramped up earlier then the other. That is, the externalsupply of Vs1 may come up before the external supply of Vs2, orconversely, the external supply of Vs2 may come up before the externalsupply of Vs 1.

Via a connection 332, voltage comparator 330 is powered by the Vs1 bus,and therefore, is not operational until Vs1 is ramped up. If Vs1 rampsup before Vs2, since voltage comparator 330 is powered by the Vs1 bus,voltage comparator 330 will control switch module 360 to route currentfrom Vs1 bus 375 to Vs2 bus 380. However, if Vs2 is ramped up earlierthan Vs1, and therefore Vs2 is greater than Vs1, there is no latch-upconcern because n-wells are tied to Vs2, and p-n junctions are reversebiased, and so, it does not matter whether switch module 360 is ON orOFF. Furthermore, when Vs1 is subsequently ramped up, since Vs2 ispreviously ramped up and is greater than Vs1, voltage comparator 330will ensure that switch module 360 is turned OFF.

FIG. 3B is a schematic of a system 300B, which is similar to system300A, but employs a single external power supply (not shown) thatprovides power, via a connection pad 385, to Vs1 voltage bus 375.Voltage level Vs2 is derived from voltage level Vs1 via a voltagegenerator 390, which may be implemented as a charge pump. Since theexternal supply provides power to Vs1 bus 375, during a power-onsequence, Vs1 is always ramped up ahead of Vs2. When Vs1 is fullyramped, voltage generator 390 creates Vs2. As in system 300A, undernormal, proper, operating conditions, Vs2>Vs1.

In system 300B, since, during power-on, Vs1 is ramped up before Vs2,voltage comparator 330 will be operational and capable of comparing Vs1to Vs2, even though Vs2 may not yet be present. Voltage comparator 330provides SW to control switch module 360 to route current from Vs1 bus375 to Vs2 bus 380 until Vs2 is greater than or equal to Vs1.

In both of system 300A and system 300B, the lower voltage supply bus,i.e., Vs1, powers voltage comparator 330. This ensures, in both ofsystems 300A and 300B, that if Vs2<Vs1, i.e., the relationship thatcould lead to a latch-up, voltage comparator 330 will control switchmodule 360 to route current from Vs1 bus 375 to Vs2 bus 380.

The concept of using a switch module to route current from a first powerbus to a second power bus can be extended to a system having more thantwo power supply levels.

FIG. 4 is a schematic of a system 400 that supplies a plurality, i.e.,“n”, of supply levels designated as Vs1 through Vsn, to respectivevoltage supply busses. Power supply pads 421, 422, 423 and 424 provide aconnection for system 400 to receive power from power supplies (notshown) for voltage levels Vs1, Vs2, Vsn−1 and Vsn, respectively. Acomparator 431 compares voltage levels Vs1 and Vs2, and via an outputSW1, controls a switch module 450. A comparator 432 compares voltagelevels Vs2 and Vs3, and provides an output SW2 that controls a switchmodule 455. There are similar comparators and switch modules betweenadjacent voltage levels up through and including a comparator 433 thatcompares voltage levels Vsn−1 and Vsn and provides an output SWn−1 forcontrolling a switch module 460.

During normal operation, Vsn>Vsn−1> . . . Vs2>Vs1, and switch modules450, 455, . . . 460 are all shut OFF. However, if a comparator thatcompares voltage levels Vsi and Vsi+1 senses a relationship ofVsi+1<Vsi, where Vsi+1 should be greater than Vsi, then the comparatorwill turn ON a corresponding switch module to route current from the Vsibus to the Vsi+1 bus. For example, if Vs3<Vs2, where Vs3 should begreater than Vs2, then comparator 432 will turn ON switch module 455 toroute current from the Vs2 bus to the Vs3 bus.

Each of the comparators in system 400 compares voltages from a lowervoltage bus and a higher voltage bus, and is powered by the lowervoltage bus. For example, (a) comparator 431 compares voltages Vs1 andVs2, and is powered by the Vs1 voltage bus, (b) comparator 432 comparesvoltages Vs2 and Vs3, and is powered by the Vs2 voltage bus, and (c)comparator 433 compares voltages Vsn−1 and Vsn, and is powered by theVsn−1 voltage bus. This ensures that in any case where the highervoltage bus has a lower voltage level than the lower voltage bus, thecomparator will be powered to control a switch for routing current fromthe lower voltage bus to the higher voltage bus.

FIG. 5 is schematic showing an embodiment of a switch module 500 forrouting current from a Vs1 bus 515 to a Vs2 bus 530. A switch moduleincludes a comparator 510 and a transmission gate 520. Comparator 510 ispowered by Vs1 bus 515.

Comparator 510 senses and compares voltage levels of Vs1 and Vs2, and ispreferably implemented as a hysteresis comparator, that is it employshysteresis to its inputs to avoid noise spike and false switching.Comparator 510 provides two outputs, SW and /SW, which are logicalcomplements of one another.

Transmission gate 520 includes an n-type device 522 and a p-type device524. An n-well of p-type device 524 is tied to Vs2 bus 530.

During normal operation, Vs2 is intended to be greater than Vs1. If Vs2is less than Vs1, then SW=1, current is routed from Vs1 bus 515 to Vs2bus 530 via n-type device 522 and p-type device 524, and thus, a forwardbiased junction of p-type device 524 is avoided. On the other hand, ifVs2 is, or becomes, greater than Vs1, then SW=0, and current is notrouted from Vs1 bus 515 to Vs2 bus 530 via transmission gate 520. WhenVs2 is greater than Vs1, since the n-well of p-type device 524 is tiedto Vs2 bus 530, the junction of p-type device 524 is reversed biased,and so, p-type device 524 does not latch-up. Switch module 500 not onlyprevents a latch-up, but also saves a significant area of siliconbecause it allows a plurality of pMOS devices to share a common n-well.

Although not illustrated herein, a CMOS circuit can be configured with aplurality on n-type devices with bodies tied to a common p-well. A powersupply switch system could also be employed to manage voltage levels insuch a CMOS circuit. The power supply switch system would comparevoltage levels of a first voltage bus and a second voltage bus, andbased on a relationship of the voltage levels, control a switch to routecurrent from the first voltage bus to the second voltage bus.

It should be understood that various alternatives, combinations andmodifications of the teachings described herein could be devised bythose skilled in the art. The present invention is intended to embraceall such alternatives, modifications and variances that fall within thescope of the appended claims.

1. A method, comprising: comparing a voltage level (Vs1) of a lowervoltage supply bus to a voltage level (Vs2) of a higher voltage supplybus; and routing current from said lower voltage supply bus to saidhigher voltage supply bus if Vs2<Vs1, wherein said lower and highervoltage supply busses provide power to a complementary metal oxidesemiconductor (CMOS) circuit.
 2. The method of claim 1, wherein saidcomparing is performed by a device that is powered by said lower voltagesupply bus.
 3. The method of claim 1, wherein said routing of saidcurrent continues until Vs2≧Vs1.
 4. The method of claim 1, wherein saidlower voltage supply bus is a first voltage supply bus, wherein saidhigher voltage supply bus is a second voltage supply bus, and whereinsaid method further comprises: comparing Vs2 to a voltage level (Vs3) ofa third voltage supply bus; and routing current from said second voltagesupply bus to said third voltage supply bus if Vs3<Vs2.
 5. The method ofclaim 4, wherein said third voltage supply bus also provides power tosaid (CMOS) circuit, and wherein said CMOS circuit operates withVs3>Vs2>Vs1.
 6. The method of claim 1, wherein said CMOS circuitincludes a plurality of p-type metal oxide semiconductor devices in acommon well.
 7. The method of claim 6, wherein said common well iselectrically connected to said higher voltage supply bus.
 8. The methodof claim 1, wherein said comparing is performed by a device havinginputs for sensing Vs1 and Vs2, and that employs hysteresis to saidinputs.
 9. A circuit, comprising: a comparator that compares a voltagelevel (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of ahigher voltage supply bus; and a switch that routes current from saidlower voltage supply bus to said higher voltage supply bus if Vs2<Vs1,wherein said lower and higher voltage supply busses provide power to acomplementary metal oxide semiconductor (CMOS) circuit.
 10. The circuitof claim 9, wherein said comparator is powered by said lower voltagesupply bus.
 11. The circuit of claim 9, wherein said switch continues toroute said current until Vs2≧Vs1.
 12. The circuit of claim 9, whereinsaid comparator is a first comparator, wherein said switch is a firstswitch, wherein said lower voltage supply bus is a first voltage supplybus, wherein said higher voltage supply bus is a second voltage supplybus, and wherein said circuit further comprises: a second comparatorthat compares Vs2 to a voltage level (Vs3) of a third voltage supplybus; and a second switch that routes current from said second voltagesupply bus to said third voltage supply bus if Vs3<Vs2.
 13. The circuitof claim 12, wherein said third voltage supply bus also provides powerto said (CMOS) circuit, and wherein said CMOS circuit operates withVs3>Vs2>Vs1.
 14. The circuit of claim 9, wherein said CMOS circuitincludes a plurality of p-type metal oxide semiconductor devices in acommon well.
 15. The circuit of claim 14, wherein said common well iselectrically connected to said higher voltage supply bus.
 16. Thecircuit of claim 9, wherein said comparator includes inputs for sensingVs1 and Vs2, and employs hysteresis to said inputs.